# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |

  define i1 @ptrtoint_s1_p0(ptr %p) {
  entry:
    %0 = ptrtoint ptr %p to i1
    ret i1 %0
  }

  define i8 @ptrtoint_s8_p0(ptr %p) {
  entry:
    %0 = ptrtoint ptr %p to i8
    ret i8 %0
  }

  define i16 @ptrtoint_s16_p0(ptr %p) {
  entry:
    %0 = ptrtoint ptr %p to i16
    ret i16 %0
  }

  define i32 @ptrtoint_s32_p0(ptr %p) {
  entry:
    %0 = ptrtoint ptr %p to i32
    ret i32 %0
  }

  define i64 @ptrtoint_s64_p0(ptr %p) {
  entry:
    %0 = ptrtoint ptr %p to i64
    ret i64 %0
  }

...
---
name:            ptrtoint_s1_p0
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
body:             |
  bb.1.entry:
    liveins: $rdi

    ; CHECK-LABEL: name: ptrtoint_s1_p0
    ; CHECK: liveins: $rdi
    ; CHECK: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; CHECK: $al = COPY [[COPY1]]
    ; CHECK: RET 0, implicit $al
    %0:gpr(p0) = COPY $rdi
    %1:gpr(s1) = G_PTRTOINT %0(p0)
    %2:gpr(s8) = G_ANYEXT %1(s1)
    $al = COPY %2(s8)
    RET 0, implicit $al

...
---
name:            ptrtoint_s8_p0
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
body:             |
  bb.1.entry:
    liveins: $rdi

    ; CHECK-LABEL: name: ptrtoint_s8_p0
    ; CHECK: liveins: $rdi
    ; CHECK: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; CHECK: $al = COPY [[COPY1]]
    ; CHECK: RET 0, implicit $al
    %0:gpr(p0) = COPY $rdi
    %1:gpr(s8) = G_PTRTOINT %0(p0)
    $al = COPY %1(s8)
    RET 0, implicit $al

...
---
name:            ptrtoint_s16_p0
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
body:             |
  bb.1.entry:
    liveins: $rdi

    ; CHECK-LABEL: name: ptrtoint_s16_p0
    ; CHECK: liveins: $rdi
    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
    ; CHECK: $ax = COPY [[COPY1]]
    ; CHECK: RET 0, implicit $ax
    %0:gpr(p0) = COPY $rdi
    %1:gpr(s16) = G_PTRTOINT %0(p0)
    $ax = COPY %1(s16)
    RET 0, implicit $ax

...
---
name:            ptrtoint_s32_p0
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
body:             |
  bb.1.entry:
    liveins: $rdi

    ; CHECK-LABEL: name: ptrtoint_s32_p0
    ; CHECK: liveins: $rdi
    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
    ; CHECK: $eax = COPY [[COPY1]]
    ; CHECK: RET 0, implicit $eax
    %0:gpr(p0) = COPY $rdi
    %1:gpr(s32) = G_PTRTOINT %0(p0)
    $eax = COPY %1(s32)
    RET 0, implicit $eax

...
---
name:            ptrtoint_s64_p0
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
body:             |
  bb.1.entry:
    liveins: $rdi

    ; CHECK-LABEL: name: ptrtoint_s64_p0
    ; CHECK: liveins: $rdi
    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
    ; CHECK: $rax = COPY [[COPY]]
    ; CHECK: RET 0, implicit $rax
    %0:gpr(p0) = COPY $rdi
    %1:gpr(s64) = G_PTRTOINT %0(p0)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...
